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DSP_blk_eswap32
4-81 C64x+ DSPLIB Reference
t2 = _x[i*4 + 1];
t3 = _x[i*4 + 0];
_r[i*4 + 0] = t0;
_r[i*4 + 1] = t1;
_r[i*4 + 2] = t2;
_r[i*4 + 3] = t3;
}
}
Special Requirements
- Input and output arrays do not overlap, except where “r == NULL” so that
the operation occurs in-place.
- The input array and output array are expected to be double-word aligned,
and a multiple of 4 words must be processed.
Implementation Notes
- Bank Conflicts: No bank conflicts occur.
- Interruptibility: The code is interrupt-tolerant but not interruptible.
Benchmarks Cycles nx/4 + 20
Codesize 116 bytes