Filter
Top Products
DSP_fir_r8_hM16_rM8A8X8
4-51 C64x+ DSPLIB Reference
Special Requirements
- The number of coefficients, nh, must be a multiple of 8 and greater than
or equal to 16. Coefficients must be in reverse order.
- The number of outputs computed, nr, must be a multiple of 8 and greater
than or equal to 8.
- Array r[ ] must be double word aligned.
Implementation Notes
- Bank Conflicts: No bank conflicts occur.
- Interruptibility: The code is interruptible.
- The load double-word instruction is used to simultaneously load four
values in a single clock cycle.
- The inner loop is unrolled 4 times and will always compute a multiple of
4 output samples.
- The outer loop is conditionally executed in parallel with the inner loop. This
allows for a zero overhead outer loop.
Benchmarks Cycles When nh>32, nh*nr/8+22
Otherwise, 32*nr/8+22
Codesize 640 bytes