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PRELIMINARY
1.6 Block Diagram 2K & 4K TDI Camera
Fairchild CAM-4k TDI.ppt 4
Fairchild Imaging
DC
BIAS
SUPP.
GEN’L
PWR
SUPP.
I / O
Buffers
25.0MHz
Hi Speed
Clock
Drivers
Timing
& I / O
Control
Low Speed
Clock
Drivers
CCD
Sensor
Analog
Buffers
Video
Processors
LVDS
Buffers
Data Out
Connectors
/
8
/
8
/
8
/
8
/
8
/
8
/
8
/
8
/
5
/
5
/
3
11
22
33
44
/
7
/
5
Outputs
+14V
+10V
+5.2A
+5.0D
+3.3D
+3.0A
-2V
-6V
H1/2/3/4 OR
V1/2/3 OX VSWx
SHP SHD
.
.
.
.
.
.
.
. .
. .
. .
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. .
. .
. .
. .
. .
. .
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. .
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J7
J8
+5.2
+3.3
+10
+3.3D+3.0A +3.3D+14V
50MHz
Master
Clock
+3.3
.
.
.
.
.
.
.
.
J5
.
.
.
.
.
.
.
.
J4
.
.
.
.
.
.
.
Input
Power
+12.0V
GND
Mode
Connector
Fairchild Imaging • CAM/CCD-2KLV.TDI & CAM/CCD-4KLV.TDI Line Scan Camera User’s Manual • Rev 073004 • 10 of 38