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Philips Semiconductors
TDA9964
12-bit, 3.0 V, 30 Msps analog-to-digital interface for CCD cameras
Objective specification Rev. 03 — 16 January 2001 7 of 23
9397 750 07918
© Philips Electronics N.V. 2001. All rights reserved.
Digital inputs
Pins: SHP, SHD and CLK (referenced to DGND)
V
IL
LOW-level input voltage 0 − 0.6 V
V
IH
HIGH-level input voltage 2.2 − 5.5 V
I
i
input current 0 ≤ V
i
≤ 5.5 V −3 − +3 µA
Z
i
input impedance f
CLK
= 30 MHz − 50 − kΩ
C
i
input capacitance f
CLK
= 30 MHz −− 2pF
Pins: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY,
OE, BLK, VSYNC
V
IL
LOW-level input voltage 0 − 0.6 V
V
IH
HIGH-level input voltage 2.2 − 5.5 V
I
i
input current 0 ≤ V
i
≤ 5.5 V −2 − +2 µA
Clamps
Global characteristics of the clamp loops
t
W(clamp)
clamp active pulse width in
number of pixels
PGA code = 255 for
maximum 4 LSB error
12 −−pixels
Input clamp (driven by CLPDM)
g
m(CDS)
CDS input clamp
transconductance
− 20 − mS
Correlated Double Sampling (CDS)
V
i(CDS)(p-p)
maximum peak-to-peak CDS
input amplitude (video signal)
V
CC
= 2.85 V 650 −−mV
V
CC
≥ 3.0 V 800 −−mV
V
reset(max)
maximum CDS input reset
pulse amplitude
500 −−mV
I
i(IN)
input current into pin IN at floating gate level tbf − tbf µA
C
i
input capacitance − 2 − pF
t
CDS(min)
CDS control pulses minimum
active time
V
i(CDS)(p-p)
= 800 mV
black to white transition in
1 pixel with 98.5%
V
i
recovery
8 −−ns
t
h(IN;SHP)
CDS input hold time (pin IN)
compared to control pulse
SHP
see Figure 3 and 4 4 −−ns
t
h(IN;SHD)
CDS input hold time (pin IN)
compared to control pulse
SHD
see Figure 3 and 4 4 −−ns
Amplifier
DR
PGA
PGA dynamic range − 24 − dB
∆G
PGA
PGA gain step 0.08 0.10 0.12 dB
Analog-to-Digital Converter (ADC)
DNL differential non linearity f
pix
= 30 MHz; ramp input −±0.5 ±0.9 LSB
Total chain characteristics (CDS + PGA + ADC)
f
pix(max)
maximum pixel frequency 30 −−MHz
Table 6: Characteristics
…continued
V
CCA
=V
CCD
= 3.0 V; V
CCO
= 2.7 V; f
pix
= 30 MHz; T
amb
=25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit