Filter
Top Products
7 - 34 C156-E097-01EN
Note:
When the TARG returns a MESSAGE REJECT message to reject an invalid or incorrect
message or when the TARG enters a BUS FREE phase as directed by a received message or
returns a message (SYNCHRONOUS DATA TRANSFER REQUEST message, for
example) in a prompt response to a received message, it can terminate the MESSAGE OUT
phase regardless of whether the ATN signal is true or false.
When the TARG detects a parity error in the received message information, the TARG can
request the INIT to retry message transmission by sending a REQ signal after sensing the ATN
signal false without having to change the bus phase (that is, while remaining in the MESSAGE
OUT phase). Upon receiving this REQ signal, the INIT must retransmit all of the same message
bytes that were transmitted in the MESSAGE OUT phase in the same sequence. If the message
consists of more than one byte, the INIT must make the ATN signal true before returning the
ACK signal for the first byte and must keep it true until the last byte is transferred.
Unless a parity error is detected, the TARG can execute the received message immediately after
its reception. If a parity error is detected, the TARG ignores that part of the message which has
been received after the detection of the parity error. Suppose that when the INIT retransmits a
series of messages in the MESSAGE OUT phase, the TARG has already executed some
messages. In this event, the TARG must handle the received messages so that no logical
contradiction will occur (for example, the TARG must ignore received messages that have
already been executed).
If the TARG receives all message information normally without detecting a parity error, the
TARG must enter an INFORMATION TRANSFER phase other than a MESSAGE OUT phase
and must send at least one byte of information in order to advise the INIT that message transfer
retry is unnecessary. However, for some types of message (ABORT and BUS DEVICE RESET,
for example), the TARG can report the normal completion of message reception by entering a
BUS FREE phase.
7.5.10 Signal requirements concerning transition between bus phases
When the SCSI bus is at a midpoint between two INFORMATION TRANSFER phases (during
the period of bus phase transition), interface signals must satisfy the requirements below.
1) The status of the BSY, SEL, REQ, and ACK signals must not change.
2) The status of the ATN and RST signals can change within the range determined by the
ATTENTION condition (see Subsection 7.6.1) or RESET condition (see Subsection 7.6.2).
3) The status of the C/D, I/O and MSG signals and the DATA BUS (DBn) can change.
However, the direction of data transfer over the DATA BUS must satisfy the following rule.
(See Figure 7.15.)