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MV64360 Interrupt Controller
http://www.motorola.com/computer/literature 2-17
2
Notes 1. The interrupting device is addressed from the MV64360 PCI
Bus 0.
2. The interrupting device is addressed from the MV64360 PCI
Bus 1.
3. The interrupting device is addressed from the MV64360
Device Bus.
GPP[18] Level Low PCI-PMC 0 INTC#, PMC 1
INTA#
2
GPP[19] Level Low PCI-PMC 0 INTD#, PMC 1
INTB#
2
GPP[20] Level Low PCI-VME INT 0 (Tsi148
LINT0#), PMCspan INT 2
1,5
GPP[21] Level Low PCI-VME INT 1 (Tsi148
LINT1#), PMCspan INT 3
1,5
GPP[22] Level Low PCI-VME INT 2 (Tsi148
LINT2#), PMCspan INT 0
1,5
GPP[23] Level Low PCI-VME INT 3 (Tsi148
LINT3#), PMCspan INT 1
1,5
3 GPP[24] Reserved for SROM
initialization active InitAct
output
GPP[25] Reserved for Watchdog
Timer WDE# output
GPP[26] Reserved for Watchdog
Timer WDNMI# output
GPP[27] Reserved for future device
interrupt
Table 2-8. MV64360 Interrupt Assignments (continued)
GPP
Group MV64360 Edge/Level Polarity Interrupt Source Notes