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Status
and
registers
DMA requests
Interrupts
ARM CPU
FIFO
MMC/SD
interface
CLK
divider
MMC/SD
card
interface
1.4SupportedUseCaseStatement
1.5IndustryStandard(s)ComplianceStatement
2PeripheralArchitecture
PeripheralArchitecture
Figure1.MMC/SDCardControllerBlockDiagram
TheMMC/SDcardcontrollersupportsthefollowingusercases:
•MMC/SDcardidentification
•MMC/SDsingle-blockreadusingCPU
•MMC/SDsingle-blockreadusingEDMA
•MMC/SDsingle-blockwriteusingCPU
•MMC/SDsingle-blockwriteusingEDMA
•MMC/SDmultiple-blockreadusingCPU
•MMC/SDmultiple-blockreadusingEDMA
•MMC/SDmultiple-blockwriteusingCPU
•MMC/SDmultiple-blockwriteusingEDMA
TheMMC/SDcardcontrollersupportsthefollowingindustrystandards(withtheexceptionnotedbelow):
•MMC(MultimediaCard)SpecificationV3.31
•SD(SecureDigital)PhysicalLayerSpecificationV1.1
Theinformationinthisdocumentassumesthatyouarefamiliarwiththesestandards.
TheMMC/SDcontrollerdoesnotsupporttheSPImodeofoperation.
TheMMC/SDcontrollerusestheMMC/SDprotocoltocommunicatewiththeMMC/SDcards.Youcan
configuretheMMC/SDcontrollertoworkasanMMCorSDcontroller,basedonthetypeofcardthe
controlleriscommunicatingwith.Figure2summarizestheMMC/SDmodeinterface.Figure3illustrates
howthecontrollerinterfacestothecardsinMMC/SDmode.
IntheMMC/SDmode,theMMCcontrollersupportsoneormoreMMC/SDcards.Regardlessofthe
numberofcardsconnected,theMMC/SDcontrollerselectsonebyusingidentificationbroadcastonthe
dataline.ThefollowingMMC/SDcontrollerpinsareused:
•CMD:Thispinisusedfortwo-waycommunicationbetweentheconnectedcardandtheMMC/SD
controller.TheMMC/SDcontrollertransmitscommandstothecardandthememorycarddrives
responsestothecommandsonthispin.
•DAT0orDAT0-3:MMCcardsonlyuseonedataline(DAT0)andSDcardsuseoneorfourdatalines.
ThenumberofDATpins(thedatabuswidth)issetbytheWIDTHbitintheMMCcontrolregister
(MMCCTL),seeSection4.1).
•CLK:ThispinprovidestheclocktothememorycardfromtheMMC/SDcontroller.
10MultimediaCard(MMC)/SecureDigital(SD)CardControllerSPRUE30B–September2006
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