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2.5DataFlowintheDataRegisters(MMCDRRandMMCDXR)
1st
2nd
3rd
4th
3
4th 3rd 2nd 1st
Support byten = ”1111”
Support byten = ”0111”
3rd
2nd
1st
3
3rd 2nd 1st
Support byten = ”0011”
1st
2nd
3
2nd 1st
0
Support byten = ”0001”
1st
3
1st
0
0
0
FIFO MMCDRR or MMCDXR registers
PeripheralArchitecture
TheCPUorEDMAcontrollercanread32bitsatatimefromtheFIFObyreadingtheMMCdatareceive
register(MMCDRR)andwrite32bitsatatimetotheFIFObywritingtotheMMCdatatransmitregister
(MMCDXR).However,sincethememorycardisan8-bitdevice,ittransmitsorreceivesonebyteata
time.Figure8andFigure9showhowthedata-sizedifferenceishandledbythedataregistersin
little-endianandbig-endianconfigurations,respectively.
Figure8.Little-EndianAccesstoMMCDXR/MMCDRRfromtheARMCPUortheEDMA
SPRUE30B–September2006MultimediaCard(MMC)/SecureDigital(SD)CardController17
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