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4.3MMCStatusRegister0(MMCST0)
Registers
TheMMCstatusregister0(MMCST0)recordsspecificeventsorerrors.Thetransitionfrom0to1oneach
bitinMMCST0cancauseaninterruptsignaltobesenttotheCPU.Ifaninterruptisdesired,setthe
correspondinginterruptenablebitintheMMCinterruptmaskregister(MMCIM).
Inmostcases,whenastatusbitisread,itiscleared.ThetwoexceptionsaretheDRRDYbitandthe
DXRDYbit;thesebitsareclearedonlyinresponsetothefunctionaleventsdescribedfortheminTable8,
orinresponsetoahardwarereset.
TheMMCstatusregister0(MMCST0)isshowninFigure20anddescribedinTable8.
Figure20.MMCStatusRegister0(MMCST0)
3116
Reserved
R-0
151312111098
ReservedTRNDNEDATEDDRRDYDXRDYReserved
R-0R-0RC-0R-0R-1R-0
76543210
CRCRSCRCRDCRCWRTOUTRSTOUTRDRSPDNEBSYDNEDATDNE
R-0R-0R-0R-0R-0R-0R-0R-0
LEGEND:R=Readonly;RC=Clearedto0whenread;-n=valueafterreset
Table8.MMCStatusRegister0(MMCST0)FieldDescriptions
BitFieldValueDescription
31-13Reserved0Reserved
12TRNDNETransferdone.
0Nodatatransferisdone.
1Datatransferofspecifiedlengthisdone.
11DATEDDAT3edgedetected.DATEDisclearedwhenreadbyCPU.
0ADAT3edgehasnotbeendetected.
1ADAT3edgehasbeendetected.
10DRRDYDatareceiveready.DRRDYisclearedto0whentheDATlogicisreset(DATRST=1inMMCCTL),
whenacommandissentwithdatareceive/transmitclear(DCLR=1inMMCCMD),orwhendatais
readfromtheMMCdatareceiveregister(MMCDRR).
0MMCDRRisnotready.
1MMCDRRisready.NewdatahasarrivedandcanbereadbytheCPUorbytheDMAcontroller.
9DXRDYDatatransmitready.DXRDYissetto1whentheDATlogicisreset(DATRST=1inMMCCTL),whena
commandissentwithdatareceive/transmitclear(DCLR=1inMMCCMD),orwhendataiswrittento
theMMCdatatransmitregister(MMCDXR).
0MMCDXRisnotready.
1MMCDXRisready.ThedatainMMCDXRhasbeentransmitted;MMCDXRcanacceptnewdatafrom
theCPUorfromtheDMAcontroller.
8Reserved0Reserved
7CRCRSResponseCRCerror.
0AresponseCRCerrorhasnotbeendetected.
1AresponseCRCerrorhasbeendetected.
6CRCRDRead-dataCRCerror.
0Aread-dataCRCerrorhasnotbeendetected.
1Aread-dataCRCerrorhasbeendetected.
SPRUE30B–September2006MultimediaCard(MMC)/SecureDigital(SD)CardController43
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