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2.6FIFOOperationDuringCardReadOperation
2.6.1EDMAReads
2.6.2CPUReads
PeripheralArchitecture
TheFIFOcontrollermanagestheactivitiesofreadingthedatainfromthecardandissuingEDMAread
events.EachtimeanEDMAreadeventisissued,anEDMAreadrequestinterruptgenerates.
Figure10providesdetailsoftheFIFOcontrollersoperation.Asdataisreceivedfromthecard,itisread
intotheFIFO.WhenthenumberofbytesofdatareceivedisequaltothelevelsetbytheFIFOLEVbitsin
MMCFIFOCTL,anEDMAreadeventisissuedandnewEDMAeventsaredisableduntiltheEDMAis
donewiththetransferissuedbythecurrentevent.DataisreadfromtheFIFObywayofMMCDRR.The
FIFOcontrollercontinuestoreadindatafromthecardwhilecheckingfortheEDMAeventtooccurorfor
theFIFOtobecomefull.OncetheEDMAeventfinishes,newEDMAeventsareenabled.IftheFIFOfills
up,theFIFOcontrollerstopstheMMC/SDcontrollerfromreadinganymoredatauntiltheFIFOisno
longerfull.
AnEDMAreadeventgenerateswhenthelastdataarrives,asdeterminedbytheMMCblocklength
register(MMCBLEN)andtheMMCnumberofblocksregister(MMCNBLK)settings.ThisEDMAevent
flushesallofthedatathatwasreadfromthecardfromtheFIFO.
EachtimeanEDMAreadeventgenerates,aninterrupt(DRRDYINT)generatesandtheDRRDYbitinthe
MMCstatusregister0(MMCST0)isalsoset.
ThesystemCPUcanalsodirectlyreadthecarddatabyreadingtheMMCdatareceiveregister
(MMCDRR).TheMMC/SDperipheralsupportsreadsthatare1,2,3,or4byteswideas,shownin
Figure8andFigure9.
Asdataisreceivedfromthecard,itisreadintotheFIFO.Whenthenumberofbytesofdatareceivedis
equaltothelevelsetbytheFIFOLEVbitsinMMCFIFOCTL,aDRRDYINTinterruptisissuedandthe
DRRDYbitintheMMCstatusregister0(MMCST0)isset.Uponreceivingtheinterrupt,theCPUquickly
readsoutthebytesreceived(equaltothelevelsetbytheFIFOLEVbits).ADRRDYINTinterruptalso
generateswhenthelastdataarrivesasdeterminedbytheMMCblocklengthregister(MMCBLEN)and
theMMCnumbersofblocksregister(MMCNBLK)settings.
SPRUE30B–September2006MultimediaCard(MMC)/SecureDigital(SD)CardController19
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