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2.7FIFOOperationDuringCardWriteOperation
2.7.1EDMAWrites
2.7.2CPUWrites
PeripheralArchitecture
TheFIFOcontrollermanagestheactivitiesofacceptingdatafromtheCPUorEDMAandpassingthedata
totheMMC/SDcontroller.TheFIFOcontrollerissuesEDMAwriteeventsasappropriate.Eachtimean
EDMAwriteeventisissued,anEDMAwriterequestinterruptgenerates.DataiswrittenintotheFIFO
throughMMCDXR.NotethattheEDMAaccesstoMMCDXRistransparent.
Figure11providesdetailsoftheFIFOcontroller'soperation.TheCPUorEDMAcontrollerwritesdatainto
theFIFO.TheFIFOpassesthedatatotheMMC/SDcontrollerwhichmanageswritingthedatatothe
card.WhenthenumberofbytesofdataintheFIFOislessthanthelevelsetbytheFIFOLEVbitsin
MMCFIFOCTL,anEDMAwriteeventisissuedandnewEDMAeventsaredisabled.TheFIFOcontroller
continuestotransferdatatotheMMC/SDcontrollerwhilecheckingfortheEDMAeventtofinishorforthe
FIFOtobecomeempty.OncetheEDMAeventfinishes,newEDMAeventsareenabled.IftheFIFO
becomesempty,theFIFOcontrollerinformstheMMC/SDcontroller.
EachtimeanEDMAwriteeventgenerates,aninterrupt(DXRDYINT)generatesandtheDXRDYbitinthe
MMCstatusregister0(MMCST0)isalsoset.
ThesystemCPUcanalsodirectlywritethecarddatabywritingtheMMCdatatransmitregister
(MMCDXR).TheMMC/SDperipheralsupportswritesthatare1,2,3,or4byteswide,asshownin
Figure8andFigure9.
TheCPUmakesuseoftheFIFOtotransferdatatothecardviatheMMC/SDcontroller.TheCPUwrites
thedatatobetransferredintoMMCDXR.AsisthecasewiththeEDMAdriventransaction,whenthe
numberofdataintheFIFOislessthanthelevelsetbytheFIFOLEVbitsinMMCFIFOCTL,aDXRDYINT
interruptgeneratesandtheDXRDYbitintheMMCstatusregister0(MMCST0)issettosignifytothe
CPUthatspaceisavailablefornewdata.
Note:Whenstartingthewritetransaction,theCPUisresponsibleforgettingtheFIFOreadyto
starttransferringdatabyfillinguptheFIFOwithdatapriortoinvoking/postingthewrite
commandtothecard.FillinguptheFIFOisarequirementsincenointerrupt/event
generatesatthestartofthewritetransfer.
SPRUE30B–September2006MultimediaCard(MMC)/SecureDigital(SD)CardController21
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