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4.5MMCInterruptMaskRegister(MMCIM)
Registers
TheMMCinterruptmaskregister(MMCIM)isusedtoenable(bit=1)ordisable(bit=0)statusinterrupts.
Ifaninterruptisenabled,thetransitionfrom0to1ofthecorrespondinginterruptbitintheMMCstatus
register0(MMCST0)cancauseaninterruptsignaltobesenttotheCPU.
TheMMCinterruptmaskregister(MMCIM)isshowninFigure22anddescribedinTable10.
Figure22.MMCInterruptMaskRegister(MMCIM)
3116
Reserved
R-0
151312111098
ReservedETRNDNEEDATEDEDRRDYEDXRDYReserved
R-0R/W-0R/W-0R/W-0R/W-0R-0
76543210
ECRCRSECRCRDECRCWRETOUTRSETOUTRDERSPDNEEBSYDNEEDATDNE
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table10.MMCInterruptMaskRegister(MMCIM)FieldDescriptions
BitFieldValueDescription
31-13Reserved0Reserved
12ETRNDNETransferdone(TRNDNE)interruptenable.
0Transferdoneinterruptisdisabled.
1Transferdoneinterruptisenabled.
11EDATEDDAT3edgedetect(DATED)interruptenable.
0DAT3edgedetectinterruptisdisabled.
1DAT3edgedetectinterruptisenabled.
10EDRRDYDatareceiveregisterready(DRRDY)interruptenable.
0Datareceiveregisterreadyinterruptisdisabled.
1Datareceiveregisterreadyinterruptisenabled.
9EDXRDYDatatransmitregister(MMCDXR)readyinterruptenable.
0Datatransmitregisterreadyinterruptisdisabled.
1Datatransmitregisterreadyinterruptisenabled.
8Reserved0Reserved
7ECRCRSResponseCRCerror(CRCRS)interruptenable.
0ResponseCRCerrorinterruptisdisabled.
1ResponseCRCerrorinterruptisenabled.
6ECRCRDRead-dataCRCerror(CRCRD)interruptenable.
0Read-dataCRCerrorinterruptisdisabled.
1Read-dataCRCerrorinterruptisenabled.
5ECRCWRWrite-dataCRCerror(CRCWR)interruptenable.
0Write-dataCRCerrorinterruptisdisabled.
1Write-dataCRCerrorinterruptisdisabled.
4ETOUTRSResponsetime-outevent(TOUTRS)interruptenable.
0Responsetime-outeventinterruptisdisabled.
1Responsetime-outeventinterruptisenabled.
46MultimediaCard(MMC)/SecureDigital(SD)CardControllerSPRUE30B–September2006
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