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ARM/EDMA reads/writes
Write Read
FIFO
8−bit x 32
(256−bit)
FIFO
EDMA event
128 or 256 bit
128 or 256 bit
EDMA event
EDMA event
the end of a
transfer
Pointer increment
or decrease
Pointer increment
or decrease
FIFO
16−bit DXR 16−bit DRR
16−bit DXR
shifter
16−bit DRR
shifter
DXR DRR
EDMA
request
is created
Transmission of data
Step 1: Set FIFO reset
Step 2: Set FIFO direction
Step 4: CPU driven transaction:
Fill the FIFO by writing to
MMCDXR (only first time)
Step 5: EDMA send xmit data
Step 6: If DXR ready is active,
FIFO −> 16−bit DXR
Reception of data
Step 3:
Step 2:
Step 1: Set FIFO reset
Set FIFO direction
If DRR ready is active,
16−bit DRR −> FIFO
Step 6: EDMA read reception data
Step 4: EDMA driven transaction
Step 5: DRRDYINT interrupt occur
Step 3: EDMA driven transaction
or every 128 or 256−bits
transmitted and DXRDYINT
interrupt is generated
when FIFO every 128 or
256−bits of data received
by FIFO
PeripheralArchitecture
Ahigh-leveloperationaldescriptionisasfollows:
•DataiswrittentotheFIFOthroughtheMMCdatatransmitregister(MMCDXR).Dataisreadfromthe
FIFOthroughtheMMCdatareceiveregister(MMCDRR).ThisistrueforboththeCPUandEDMA
driventransactions;however,fortheEDMAtransaction,theEDMAaccesstotheFIFOistransparent.
•TheACCWDbitsintheMMCFIFOcontrolregister(MMCFIFOCTL)determinesthebehaviorofthe
FIFOfull(FIFOFUL)andFIFOempty(FIFOEMP)statusflagsintheMMCstatusregister1(MMCST1):
–IfACCWD=00b:
•FIFOfullisactivewhenthewritepointer+4>readpointer
•FIFOemptyisactivewhenthewritepointer-4<readpointer
–IfACCWD=01b:
•FIFOfullisactivewhenthewritepointer+3>readpointer
•FIFOemptyisactivewhenthewritepointer-3<readpointer
–IfACCWD=10b:
•FIFOfullisactivewhenthewritepointer+2>readpointer
•FIFOemptyisactivewhenthewritepointer-2<readpointer
–IfACCWD=11b:
•FIFOfullisactivewhenthewritepointer+1>readpointer
•FIFOemptyisactivewhenthewritepointer-1<readpointer
Figure7.FIFOOperationDiagram
MultimediaCard(MMC)/SecureDigital(SD)CardController 16SPRUE30B–September2006
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