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4.2MMCMemoryClockControlRegister(MMCCLK)
Registers
TheMMCmemoryclockcontrolregister(MMCCLK)isusedto:
•SelectwhethertheCLKpinisenabledordisabled(CLKENbit).
•Selecthowmuchthefunctionclockisdivided-downtoproducethememoryclock(CLKRTbits).When
theCLKpinisenabled,theMMCcontrollerdrivesthememoryclockonthispintocontrolthetimingof
communicationswithattachedmemorycards.Formoredetailsaboutclockgeneration,see
Section2.1.
TheMMCmemoryclockcontrolregister(MMCCLK)isshowninFigure19anddescribedinTable7.
Figure19.MMCMemoryClockControlRegister(MMCCLK)
3116
Reserved
R-0
159870
ReservedCLKENCLKRT
R-0R/W-0R/W–FFh
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table7.MMCMemoryClockControlRegister(MMCCLK)FieldDescriptions
BitFieldValueDescription
31-9Reserved0Reserved
8CLKENCLKpinenable.
0CLKpinisdisabledandfixedlow.
1TheCLKpinisenabled;itshowsthememoryclocksignal.
7-0CLKRT0–FFhClockrate.Usethisfieldtosetthedivide-downvalueforthememoryclock.Thefunctionclockis
divideddownasfollowstoproducethememoryclock:
memoryclockfrequency=functionclockfrequency/(2×(CLKRT+1))
MultimediaCard(MMC)/SecureDigital(SD)CardController 42SPRUE30B–September2006
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