Filter
Top Products
www.ti.com
4.13MMCCommandRegister(MMCCMD)
Registers
Note:WritingtotheMMCcommandregister(MMCCMD)causestheMMCcontrollertosendthe
programmedcommand.Therefore,theMMCargumentregister(MMCARGHL)mustbe
loadedproperlybeforeawritetoMMCCMD.
TheMMCcommandregister(MMCCMD)specifiesthetypeofcommandtobesentanddefinesthe
operation(command,response,additionalactivity)fortheMMCcontroller.ThecontentofMMCCMDis
keptafterthetransfertothetransmitshiftregister.
WhentheARMwritestoMMCCMD,theMMCcontrollersendstheprogrammedcommand,includingany
argumentsintheMMCargumentregister(MMCARGHL).Fortheformatofacommand(index,arguments,
andotherbits),seeFigure31andTable19.
TheMMCcommandregister(MMCCMD)isshowninFigure30anddescribedinTable18.
Figure30.MMCCommandRegister(MMCCMD)
3124
Reserved
R-0
231716
ReservedDMATRIG
R-0R/W-0
15141312111098
DCLRINITCKWDATXSTRMTPDTRWRSPFMTBSYEXP
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
7650
PPLENReservedCMD
R/W-0R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table18.MMCCommandRegister(MMCCMD)FieldDescriptions
BitFieldValueDescription
31-17Reserved0Reserved
16DMATRIGDMAtransfereventgenerationenable.
0DMAtransfereventgenerationisdisabled.
1DMAtransfereventgenerationisenabled.
15DCLRDatareceive/transmitclear.Usethisbittoclearthedatareceiveready(DRRDY)bitandthedata
transmitready(DXRDY)bitintheMMCstatusregister0(MMCST0)beforeanewreadorwrite
sequence.Thisclearsanypreviousstatus.
0DonotclearDRRDYandDXRDYbitsinMMCST0.
1ClearDRRDYandDXRDYbitsinMMCST0.
14INITCKInitializationclockcycles.
0Donotinsertinitializationclockcycles.
1Insertinitializationclockcycles;insert80CLKcyclesbeforesendingthecommandspecifiedintheCMD
bits.Thesedummyclockcyclesarerequiredforresettingacardafterpoweron.
13WDATXDatatransferindicator.
0Thereisnodatatransfer.
1Thereisadatatransferassociatedwiththecommand.
52MultimediaCard(MMC)/SecureDigital(SD)CardControllerSPRUE30B–September2006
SubmitDocumentationFeedback