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Start
bit
End
bit
CMD
Data
CLK
1 transfer
source bit
2 CRC
bytes
2.4DataFlowintheInput/OutputFIFO
PeripheralArchitecture
Figure6.MMC/SDModeReadSequenceTimingDiagram
Table3.MMC/SDModeReadSequence
Portionofthe
SequenceDescription
RDCMDReadcommand:A6-byteREAD_SINGLE_BLOCKcommandtokenissentfromtheARMtothecard.
CMDRSPCommandresponse:ThecardsendsaresponseoftypeR1toacknowledgetheREAD_SINGLE_BLOCK
commandtotheARM.
DATBLKDatablock:ThecardsendsablockofdatatotheARM.Thedatacontentisprecededbyastartbitandis
followedbytwoCRCbyteandanendbit.
TheMMC/SDcontrollercontainsasingle256-bitFIFOthatisusedforbothreadingdatafromthememory
cardandwritingdatatothememorycard(seeFigure7).TheFIFOisorganizedas32eight-bitentries.
Theconversionfromthe32-bitbustothebyteformatoftheFIFOfollowsthelittle-endianconvention
(detailsareprovidedinlatersections).ThereadandwriteFIFOsactasaninterimlocationtostoredata
transferredfrom/tothecardmomentarilyviatheCPUorEDMA.TheFIFOincludeslogictogenerate
EDMAeventsandinterruptsbasedontheamountofdataintheFIFOandaprogrammablenumberof
bytesreceived/transmitted.FlagsaresetwhentheFIFOisfullorempty.
SPRUE30B–September2006MultimediaCard(MMC)/SecureDigital(SD)CardController15
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