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H8DI3+/I+(-F) Serverboard User’s Manual
DRAM ECC Enable
This setting allows hardware to report and correct memory errors
automatically, maintaining system integrity. Options are Enabled or
Disabled.
DRAM Scrub Redirect
This setting allows the system to correct DRAM ECC errors immedi-
ately when they occur, even if background scrubbing is off. Options are
Enabled or Disabled.
4-Bit ECC Mode
This setting enables 4-Bit ECC mode (also known as CHIPKILL ECC
Mode). Options are Enabled or Disabled.
DRAM BG Scrub
DRAM scrubbing corrects memory errors so later reads are correct.
Doing this while memory is not being used improves performance.
Options are Disabled and time increments from 40ns to 655.4us with
163.8us the default.
Note: When AMD's Node Interleave feature is enabled, the BIOS will
force DRAM scrub off.
DATA Cache BG Scrub
This setting allows L1 data cache RAM to be corrected while idle.
Options are Disabled and time increments from 40ns to 655.4us with
2.5us the default.
L2 Cache BG Scrub
This setting allows L2 data cache RAM to be corrected while idle.
Options are Disabled and time increments from 40ns to 655.4us with
2.5us the default.
L3 Cache BG Scrub
This setting allows L3 data cache RAM to be corrected while idle.
Options are Disabled and time increments from 40ns to 655.4us with
2.5us the default.