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68 © 2007 VBrick Systems, Inc.
Status: Encoder Status
This menu allows users to view vital Encoder statistics. As you Refresh you should see
Transmit State – Transmitting and the IP Bytes Transferred count should increment. If this
does not happen check your VBrick's encoder configuration or network.
Source IP Address The IP Address of the video source.
Bytes Transferred The number of receive bytes transferred.
Buffer Full Count The number of times the decoder buffer filled to capacity.
Decoder Sync
State
Indicates whether the MPEG-2 transport layer has achieved its
synchronization. Most likely indicates a configuration or network
problem.
Lost Sync Count The number of times the decoder has acquired synchronization with
the transport stream (see note under Unexpected Fragments).
Packets Received The count of IP packets received.
Non Video Packet The count of packets directed to this decoder, which are not part of
the video stream.
Unexpected
Fragments
The number of mis-ordered packets received. Each appliance
maintains a statistical report on Unexpected Fragments received from
a particular video stream. Note: If multiple devices in the same unit
(i.e. decoder or hard disk) are tuned to the same stream, the
Unexpected Fragments count on Slot1 is used exclusively to report
statistical results.
Packet Ordering Packet ordering status. Packet ordering is temporarily disabled under
conditions, such as the IP ID is not increasing or disabled, or the
access method does not support reordering. Packets arriving over
Ethernet can be reordered.
Jitter Queue Status Status of the jitter Q. It is generally equal to the value of the Jitter
Queue of the decoder with the following exception: if a variable
transport (video, audio and idle frames included) rate stream is being
decoded then the jitter queue will be temporarily disabled. The Jitter
Queue will be re-enabled when the decoder senses that a video stream
of fixed rate transport is being received.
Audio Micro-code
Revision
Revision of the audio microcode on the decoder chip.
Video Micro-code
Revision
Revision of the video microcode on the decoder chip.
FPGA Revision Revision of the FPGA chip on the decoder daughter card.
CPLD Revision Revision level of the CPLD on the decoder daughter card.
PLX EEPROM
Revision
Revision level of the PLX EEPROM on the decoder daughter card.