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6−4
6.3 Socket Present State Register
This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see
Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card V
CC
support
and card type is only updated at each insertion. Also note that the PCI7x21/PCI7x11 controller uses the CCD1
and
CCD2
signals during card identification, and changes on these signals during this operation are not reflected in this
register.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Socket present state
Type R R R R R R R R R R R R R R R R
Default 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Socket present state
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X
Register: Socket present state
Offset: CardBus Socket Address + 08h
Type: Read-only
Default: 3000 00XXh
Table 6−4. Socket Present State Register Description
BIT SIGNAL TYPE FUNCTION
31 YVSOCKET R
YV socket. This bit indicates whether or not the socket can supply V
CC
= Y.Y V to PC Cards. The
PCI7x21/PCI7x11 controller does not support Y.Y-V V
CC
; therefore, this bit is always reset unless
overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
30 XVSOCKET R
XV socket. This bit indicates whether or not the socket can supply V
CC
= X.X V to PC Cards. The
PCI7x21/PCI7x11 controller does not support X.X-V V
CC
; therefore, this bit is always reset unless
overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.
29 3VSOCKET R
3-V socket. This bit indicates whether or not the socket can supply V
CC
= 3.3 Vdc to PC Cards. The
PCI7x21/PCI7x11 controller does support 3.3-V V
CC
; therefore, this bit is always set unless overridden
by the socket force event register (offset 0Ch, see Section 6.4).
28 5VSOCKET R
5-V socket. This bit indicates whether or not the socket can supply V
CC
= 5 Vdc to PC Cards. The
PCI7x21/PCI7x11 controller does support 5-V V
CC
; therefore, this bit is always set unless overridden
by bit 6 of the device control register (PCI offset 92h, see Section 4.39).
27−14 RSVD R These bits return 0s when read.
13 † YVCARD R
YV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= Y.Y Vdc.
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
12 † XVCARD R
XV card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= X.X Vdc.
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
11 † 3VCARD R
3-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= 3.3 Vdc.
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
10 † 5VCARD R
5-V card. This bit indicates whether or not the PC Card inserted in the socket supports V
CC
= 5 Vdc.
This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
†
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST
when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST
or GRST.