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1.2 Features
The PCI7x21/PCI7x11 controller supports the following features:
• PC Card Standard 8.1 compliant
• PCI Bus Power Management Interface Specification 1.1 compliant
• Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant
• PCI Local Bus Specification Revision 2.3 compliant
• PC 98/99 and PC2001 compliant
• Windows Logo Program 2.0 compliant
• PCI Bus Interface Specification for PCI-to-CardBus Bridges
• Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std
1394a-2000
• Fully compliant with 1394 Open Host Controller Interface Specification 1.1
• 1.5-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.5-V core V
CC
• Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Supports PC Card or CardBus with hot insertion and removal
• Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus
• Supports serialized IRQ with PCI interrupts
• Programmable multifunction terminals
• Many interrupt modes supported
• Serial ROM interface for loading subsystem ID and subsystem vendor ID
• ExCA-compatible registers are mapped in memory or I/O space
• Intel 82365SL-DF register compatible
• Supports ring indicate, SUSPEND
, and PCI CLKRUN protocols
• Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals
• Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394
• Compliant with Intel Mobile Power Guideline 2000
• Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed
concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume
• Power-down features to conserve energy in battery-powered applications include: automatic device power
down during suspend, PCI power management for link-layer, and inactive ports powered down,
ultralow-power sleep mode
• Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s
• Cable ports monitor line conditions for active connection to remote node
• Cable power presence monitoring
• Separate cable bias (TPBIAS) for each port
• Physical write posting of up to three outstanding transactions
• PCI burst transfers and deep FIFOs to tolerate large host latency