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8.45 Isochronous Receive Context Command Pointer Register
The isochronous receive context command pointer register contains a pointer to the address of the first descriptor
block that the PCI7x21/PCI7x11 controller accesses when software enables an isochronous receive context by
setting bit 15 (run) in the isochronous receive context control register (see Section 8.44) to 1. The n value in the
following register addresses indicates the context number (n = 0, 1, 2, 3).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Isochronous receive context command pointer
Type R R R R R R R R R R R R R R R R
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Isochronous receive context command pointer
Type R R R R R R R R R R R R R R R R
Default X X X X X X X X X X X X X X X X
Register: Isochronous receive context command pointer
Offset: 40Ch + (32 * n)
Type: Read-only
Default: XXXX XXXXh