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Table 6−5. Socket Force Event Register Description
BIT SIGNAL TYPE FUNCTION
31−15 RSVD R Reserved. These bits return 0s when read.
14 CVSTEST W
Card VS test. When this bit is set, the PCI7x21/PCI7x11 controller reinterrogates the PC Card, updates
the socket present state register (offset 08h, see Section 6.3), and re-enables the socket power control.
13 FYVCARD W
Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
12 FXVCARD W
Force XV card. Writes to this bit cause the XVCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
11 F3VCARD W
Force 3-V card. Writes to this bit cause the 3VCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
10 F5VCARD W
Force 5-V card. Writes to this bit cause the 5VCARD bit in the socket present state register (offset 08h,
see Section 6.3) to be written. When set, this bit disables the socket power control.
9 FBADVCCREQ W
Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register (offset 08h,
see Section 6.3) can be made by writing this bit.
8 FDATALOST W
Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register (offset
08h, see Section 6.3) to be written.
7 FNOTACARD W
Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
6 RSVD R This bit returns 0 when read.
5 FCBCARD W
Force CardBus card. Writes to this bit cause the CBCARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
4 F16BITCARD W
Force 16-bit card. Writes to this bit cause the 16BITCARD bit in the socket present state register (offset
08h, see Section 6.3) to be written.
3 FPWRCYCLE W
Force power cycle. Writes to this bit cause the PWREVENT bit in the socket event register (offset 00h,
see Section 6.1) to be written, and the PWRCYCLE bit in the socket present state register (offset 08h,
see Section 6.3) is unaffected.
2 FCDETECT2 W
Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register (offset 00h, see
Section 6.1) to be written, and the CDETECT2 bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.
1 FCDETECT1 W
Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register (offset 00h, see
Section 6.1) to be written, and the CDETECT1 bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.
0 FCARDSTS W
Force CSTSCHG. Writes to this bit cause the CSTSEVENT bit in the socket event register (offset 00h,
see Section 6.1) to be written. The CARDSTS bit in the socket present state register (offset 08h, see
Section 6.3) is unaffected.