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8−2
Table 8−1. OHCI Register Map (Continued)
DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET
Self-ID Reserved — 60h
Self-ID buffer pointer SelfIDBuffer 64h
Self-ID count SelfIDCount 68h
Reserved — 6Ch
—
Isochronous receive channel mask high
IRChannelMaskHiSet 70h
Isochronous receive channel mask high
IRChannelMaskHiClear 74h
Isochronous receive channel mask low
IRChannelMaskLoSet 78h
Isochronous receive channel mask low
IRChannelMaskLoClear 7Ch
Interrupt event
IntEventSet 80h
Interrupt event
IntEventClear 84h
Interrupt mask
IntMaskSet 88h
Interrupt mask
IntMaskClear 8Ch
Isochronous transmit interrupt event
IsoXmitIntEventSet 90h
Isochronous transmit interrupt event
IsoXmitIntEventClear 94h
Isochronous transmit interrupt mask
IsoXmitIntMaskSet 98h
Isochronous transmit interrupt mask
IsoXmitIntMaskClear 9Ch
—
Isochronous receive interrupt event
IsoRecvIntEventSet A0h
Isochronous receive interrupt event
IsoRecvIntEventClear A4h
Isochronous receive interrupt mask
IsoRecvIntMaskSet A8h
Isochronous receive interrupt mask
IsoRecvIntMaskClear ACh
Initial bandwidth available InitialBandwidthAvailable B0h
Initial channels available high InitialChannelsAvailableHi B4h
Initial channels available low InitialChannelsAvailableLo B8h
Reserved — BCh−D8h
Fairness control FairnessControl DCh
Link control ‡
LinkControlSet E0h
Link control ‡
LinkControlClear E4h
Node identification NodeID E8h
PHY layer control PhyControl ECh
Isochronous cycle timer Isocyctimer F0h
Reserved — F4h−FCh
Asynchronous request filter high
AsyncRequestFilterHiSet 100h
Asynchronous request filter high
AsyncRequestFilterHiClear 104h
Asynchronous request filter low
AsyncRequestFilterLoSet 108h
Asynchronous request filter low
AsyncRequestFilterLoClear 10Ch
Physical request filter high
PhysicalRequestFilterHiSet 110h
Physical request filter high
PhysicalRequestFilterHiClear 114h
Physical request filter low
PhysicalRequestFilterLoSet 118h
Physical request filter low
PhysicalRequestFilterLoClear 11Ch
Physical upper bound PhysicalUpperBound 120h
Reserved — 124h−17Ch
‡
One or more bits in this register are cleared only by the assertion of GRST
.