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8−39
8.41 Asynchronous Context Command Pointer Register
The asynchronous context command pointer register contains a pointer to the address of the first descriptor block
that the PCI7x21/PCI7x11 controller accesses when software enables the context by setting bit 15 (run) in the
asynchronous context control register (see Section 8.40) to 1. See Table 8−32 for a complete description of the
register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Asynchronous context command pointer
Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Asynchronous context command pointer
Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU
Default X X X X X X X X X X X X X X X X
Register: Asynchronous context command pointer
Offset: 18Ch [ATRQ]
1ACh [ATRS]
1CCh [ARRQ]
1ECh [ARRS]
Type: Read/Write/Update
Default: XXXX XXXXh
Table 8−32. Asynchronous Context Command Pointer Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−4 descriptorAddress RWU Contains the upper 28 bits of the address of a 16-byte aligned descriptor block.
3−0 Z RWU Indicates the number of contiguous descriptors at the address pointed to by the descriptor address.
If Z is 0, then it indicates that the descriptorAddress field (bits 31−4) is not valid.