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13−5
13.5 Class Code and Revision ID Register
The class code and revision ID register categorizes the base class, subclass, and programming interface of the
function. The base class is 07h, identifying the controller as a communication device. The subclass is 80h, identifying
the function as other mass storage controller, and the programming interface is 00h. Furthermore, the TI chip revision
is indicated in the least significant byte (00h). See Table 13−4 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Class code and revision ID
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Class code and revision ID
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Class code and revision ID
Offset: 08h
Type: Read-only
Default: 0780 0000h
Table 13−4. Class Code and Revision ID Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−24 BASECLASS R Base class. This field returns 07h when read, which classifies the function as a communication device.
23−16 SUBCLASS R Subclass. This field returns 80h when read, which specifically classifies the function as other mass
storage controller.
15−8 PGMIF R Programming interface. This field returns 00h when read.
7−0 CHIPREV R Silicon revision. This field returns 00h when read, which indicates the silicon revision of the Smart Card
controller.
13.6 Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size
and the latency timer associated with the Smart Card controller. See Table 13−5 for a complete description of the
register contents.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Latency timer and class cache line size
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Latency timer and class cache line size
Offset: 0Ch
Type: Read/Write
Default: 0000h
Table 13−5. Latency Timer and Class Cache Line Size Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the Smart Card controller,
in units of PCI clock cycles. When the Smart Card controller is a PCI bus initiator and asserts FRAME
,
the latency timer begins counting from zero. If the latency timer expires before the Smart Card
transaction has terminated, then the Smart Card controller terminates the transaction when its GNT
is deasserted.
7−0 CACHELINE_SZ RW Cache line size. This value is used by the Smart Card controller during memory write and invalidate,
memory-read line, and memory-read multiple transactions.