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Table 2−13. CardBus PC Card Address and Data Terminals
External components are not applicable for the 16-bit PC Card address and data terminals. If any CardBus PC Card
address and data terminal is unused, then the terminal may be left floating.
SKT A TERMINAL SKT B TERMINAL
†
DESCRIPTION
I/O
INPUT
OUTPUT
POWER
NAME NO. NAME NO.
DESCRIPTION
I/O
TYPE
INPUT OUTPUT
POWER
RAIL
A_CAD31
A_CAD30
A_CAD29
A_CAD28
A_CAD27
A_CAD26
A_CAD25
A_CAD24
A_CAD23
A_CAD22
A_CAD21
A_CAD20
A_CAD19
A_CAD18
A_CAD17
A_CAD16
A_CAD15
A_CAD14
A_CAD13
A_CAD12
A_CAD11
A_CAD10
A_CAD9
A_CAD8
A_CAD7
A_CAD6
A_CAD5
A_CAD4
A_CAD3
A_CAD2
A_CAD1
A_CAD0
D01
C01
D03
C02
B01
B04
A04
E06
B05
C06
B06
G09
C07
B07
A07
A10
E11
G11
C11
B11
C12
B12
A12
E12
C13
F12
A13
C14
E13
A14
B14
E14
B_CAD31
B_CAD30
B_CAD29
B_CAD28
B_CAD27
B_CAD26
B_CAD25
B_CAD24
B_CAD23
B_CAD22
B_CAD21
B_CAD20
B_CAD19
B_CAD18
B_CAD17
B_CAD16
B_CAD15
B_CAD14
B_CAD13
B_CAD12
B_CAD11
B_CAD10
B_CAD9
B_CAD8
B_CAD7
B_CAD6
B_CAD5
B_CAD4
B_CAD3
B_CAD2
B_CAD1
B_CAD0
B15
A16
B16
A17
C16
D17
C19
D18
E17
E19
G15
F18
H14
H15
G17
K17
L13
K18
L15
L17
L18
L19
M17
M14
M15
N19
N18
N15
M13
P18
P17
P19
CardBus address and data. These signals make up the multiplexed
CardBus address and data bus on the CardBus interface. During
the address phase of a CardBus cycle, CAD31−CAD0 contain a
32-bit address. During the data phase of a CardBus cycle,
CAD31−CAD0 contain data. CAD31 is the most significant bit.
I/O
PCII7 PCIO7
V
CCA
/
V
CCB
A_CC/BE3
A_CC/BE2
A_CC/BE1
A_CC/BE0
C05
F09
B10
G12
B_CC/BE3
B_CC/BE2
B_CC/BE1
B_CC/BE0
F15
G18
K14
M18
CardBus bus commands and byte enables. CC/BE3−CC/BE0 are
multiplexed on the same CardBus terminals. During the address
phase of a CardBus cycle, CC/BE3
−CC/BE0 define the bus
command. During the data phase, this 4-bit bus is used as byte
enables. The byte enables determine which byte paths of the full
32-bit data bus carry meaningful data. CC/BE0
applies to byte 0
(CAD7−CAD0), CC/BE1
applies to byte 1 (CAD15−CAD8),
CC/BE2
applies to byte 2 (CAD23−CAD16), and CC/BE3 applies to
byte 3 (CAD31−CAD24).
I/O
PCII7 PCIO7
V
CCA
/
V
CCB
A_CPAR G10 B_CPAR K13
CardBus parity. In all CardBus read and write cycles, the controller
calculates even parity across the CAD and CC/BE
buses. As an
initiator during CardBus cycles, the controller outputs CPAR with a
one-CCLK delay. As a target during CardBus cycles, the controller
compares its calculated parity to the parity indicator of the initiator;
a compare error results in a parity error assertion.
I/O
PCII7 PCIO7
V
CCA
/
V
CCB
†
These terminals are reserved for the PCI7611 and PCI7411 controllers.