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3−3
3.4.2 Device Resets
The following are the requirements for proper reset of the PCI7x21/PCI7x11 controller:
1. GRST
and PRST must both be asserted at power on.
2. GRST
must be asserted for at least 2 ms at power on
3. PRST
must be deasserted either at the same time or after GRST is asserted
4. PCLK must be stable for 100 µs before PRST
is deasserted.
VCC
GRST
PRST
PCLK
> 2 ms > 0 ns
> 100 ms
Figure 3−3. PCI Reset Requirement
3.4.3 Serial EEPROM I
2
C Bus
The PCI7x21/PCI7x11 controller offers many choices for modes of operation, and these choices are selected by
programming several configuration registers. For system board applications, these registers are normally
programmed through the BIOS routine. For add-in card and docking-station/port-replicator applications, the
PCI7x21/PCI7x11 controller provides a two-wire inter-integrated circuit (IIC or I
2
C) serial bus for use with an external
serial EEPROM.
The PCI7x21/PCI7x11 controller is always the bus master, and the EEPROM is always the slave. Either device can
drive the bus low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors
on the SCL and SDA signal lines. The PCI7x21/PCI7x11 controller is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and
SDA terminals. If the PCI7x21/PCI7x11 controller detects a logic-high level on the SCL terminal at the end of GRST
,
then it initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I
2
C limit of 16 Kbits
can be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the PCI7x21/PCI7x11
controller. Figure 3−3 shows a serial EEPROM application.
In addition to loading configuration data from an EEPROM, the PCI7x21/PCI7x11 I
2
C bus can be used to read and
write from other I
2
C serial devices. A system designer can control the I
2
C bus, using the PCI7x21/PCI7x11 controller