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12−15
12.23 Subsystem Access Register
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 2Ch and 2Eh, respectively. See Table 12−16 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Subsystem access
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Subsystem access
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Subsystem access
Offset: 8Ch
Type: Read/Write
Default: 0000 0000h
Table 12−16. Subsystem Access Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−16 SubsystemID RW Subsystem device ID. The value written to this field is aliased to the subsystem ID register at
PCI offset 2Eh.
15−0 SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 2Ch.
12.24 Diagnostic Register
This register enables the diagnostic modes. See Table 12−17 for a complete description of the register contents. All
bits in this register are reset by GRST
only.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Diagnostic
Type R R R R R R R R R R R R R R R RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Diagnostic
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Diagnostic
Type: Read-only, Read/Write
Offset: 90h
Default: 0000 0000h
Table 12−17. Diagnostic Register Description
BIT SIGNAL TYPE FUNCTION
31−17 RSVD R Reserved. Bits 31−17 return 0s when read.
16 DIAGNOSTIC RW Diagnostic test bit. This test bit shortens the card detect debounce times for simulation and TDL.
15−0 RSVD R Reserved. Bits 15−0 return 0s when read.