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B_CCLKRUN
//B_WP
(IOIS16
)
W
P
D
A
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T
U
V
M
N
K
L
H
J
F
G
E
B
C
19151051 14131211 169876432 17 18
A_CINT//
A_READY
(IREQ
)
A_CAD25
//A_A1
VCCA
A_CAD21
//A_A5
A_CAD19
//A_A25
A_CC/BE2
//A_A12
A_CDEVSEL
//A_A21
A_CPAR
//A_A13
VCCA
A_CAD11
//A_OE
A_CAD8
//A_D15
A_RSVD
//A_D14
A_CAD3
//A_D5
A_CAD0
//A_D3
B_CAD30
//B_D9
B_CAD27
//B_D0
B_CSTSCHG
//B_BVD1
(STSCHG
/RI)
A_CAUDIO
//A_BVD2
(SPKR
)
A_CSERR
//A_WAIT
A_CAD26
//A_A0
A_CC/BE3
//A_REG
A_CAD22
//A_A4
A_CAD20
//A_A6
A_CAD17
//A_A24
A_CCLK
//A_A16
A_CBLOCK
//A_A19
A_CAD16
//A_A17
A_CAD12
//A_A11
A_CC/BE0
//A_CE1
A_CAD6
//A_D13
A_CAD4
//A_D12
A_CCD1
//A_CD1
B_CAD28
//B_D8
B_CSERR
//B_WAIT
B_CINT
//B_READY
(IREQ)
A_CCD2
//A_CD2
A_CCLKRUN
//A_WP
(IOIS16)
A_CSTSCHG
//A_BVD1
(STSCHG
/RI)
A_CVS1
//A_VS1
A_CAD23
//A_A3
A_CRST
//A_RESET
A_CAD18
//A_A7
A_CTRDY
//A_A22
A_CPERR
//A_A14
A_CC/BE1
//A_A8
A_CAD13
//A_IORD
A_CAD9
//A_A10
A_CAD5
//A_D6
A_CAD2
//A_D11
B_RSVD
//B_D2
B_CCD2
//B_CD2
B_CAUDIO
//B_BVD2
(SPKR
)
B_CVS1
//B_VS1
B_CAD24
//B_A2
A_CAD30
//A_D9
A_CAD29
//A_D1
A_CAD28
//A_D8
B_CAD25
//B_A1
B_CC/BE3
//B_REG
VCCB
B_USB_EN
A_CAD31
//A_D10
A_CAD27
//A_D0
A_CAD24
//A_A2
A_CVS2
//A_VS2
A_CFRAME
//A_A23
A_CGNT
//A_WE
A_RSVD
//A_A18
A_CAD10
//A_CE2
A_CAD7
//A_D7
B_CAD31
//B_D10
B_CAD29
//B_D1
B_CREQ
//B_INPACK
B_CAD22
//B_A4
B_CRST
//B_RESET
MS_BS//
SD_CMD
//SM_WE
A_RSVD
//A_D2
A_CREQ
//A_INPACK
A_CIRDY
//A_A15
A_CAD14
//A_A9
A_CAD1
//A_D4
B_CAD26
//B_A0
B_CAD23
//B_A3
B_CAD20
//B_A6
B_CVS2
//B_VS2
B_CAD18
//B_A7
MS_DATA1
//SD_DAT1
//SM_D1
MS_CLK//
SD_CLK//
SM_EL_WP
VCC
VCC
A_CSTOP
//A_A20
A_CAD15
//A_IOWR
VCC
VCC
VCC
B_CAD21
//B_A5
B_CC/BE2
//B_A12
B_CFRAME
//B_A23
B_CIRDY
//B_A15
SD_CLK
//SM_RE
SD_CMD//
SM_ALE
SM_R/B
GND GND
VCC
GND
VCC
B_CTRDY
//B_A22
B_CAD19
//B_A25
B_CAD17
//B_A24
B_CCLK
//B_A16
B_CDEVSEL
//B_A21
B_CGNT
//B_WE
SD_DAT2
//SM_D6
SD_WP//
SM_CE
RSVD
SM_PHYS
_WP
VCC
GND
GND GND
GND
B_CPERR
//B_A14
B_CSTOP
//B_A20
B_CBLOCK
//B_A19
B_CPAR
//B_A13
VR_
PORT
RSVD
RSVD
VR_
PORT
SCL
VCC
GND
GND GND VCC
B_CAD15
//B_IOWR
B_CAD14
//B_A9
B_RSVD
//B_A18
B_CC/BE1
//B_A8
B_CAD16
//B_A17
VCCB
VR_EN
CLK_48 SDA
CLOCK
MFUNC1
SPKROUT
GND
GND GND GND GND
B_CAD7
//B_D7
B_CAD10
//B_CE2
B_CAD13
//B_IORD
B_CAD12
//B_A11
B_CAD11
//B_OE
DATA LATCH
MFUNC0 MFUNC5
VCC
GND
NC
AGND
VCC
TEST0
VCC
B_CAD4
//B_D12
B_CAD3
//B_D5
B_CC/BE0
//B_CE1
B_CAD9
//B_A10
B_CAD8
//B_D15
MFUNC2 MFUNC4MFUNC3
GRST
AD17
VCC
PAR
AD12
AD2
PC0
(TEST1)
RSVD
B_CCD1
//B_CD1
B_CAD6
//B_D13
B_CAD5
//B_D6
B_RSVD
//B_D14
MFUNC6
SUSPEND
PRST
AD30 AD26
C/BE1
CPS
RSVD
RSVD
B_CAD0
//B_D3
B_CAD2
//B_D11
B_CAD1
//B_D4
PCLK
GNT
RI_OUT
//PME
AD21
C/BE2
DEVSEL
AD11
AD6
AD1
AVDD
AGND
RSVD
PHY_
TEST_
MA
CNA
REQ
AD31
AD27
VSSPLL
XI
XO
AD29
AD28
AD24
AD22
AD18
IRDY
PERR
AD14
VDPLL
_33
C/BE0
AD3
PC1
(TEST2)
VSSPLL
TPBIAS0
AVDD
RSVD
VDPLL
_15
VCCP
AD25
IDSEL
AD20
AD16 TRDY
SERR
AD13
AD10
AD8
AD4
PC2
(TEST3)
TPB0P TPA0P
R1
TPB1P AVDD TPA1P
TPBIAS1
C/BE3
AD23
AD19
FRAME
STOP
AD15
VCCP
AD9
AD7
AD5
AD0 TPB0N TPA0N
R0
TPB1N
AGND
TPA1N
MC_PWR
_CTRL_0
MS_SDIO
(DATA0)//
SD_DAT0//
SM_D0
SM_CLE
A_USB_EN
MC_PWR
_CTRL_1
MS_DATA2
//SD_DAT2
//SM_D2
SD_DAT0
//SM_D4
MS_DATA3//
SD_DAT3
//SM_D3
SD_DAT3
//SM_D7
SD_DAT1
//SM_D5
SD_CD
MS_CD SM_CD
Figure 2−2. PCI7421 GHK/ZHK-Package Terminal Diagram