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8−27
8.30 Fairness Control Register
The fairness control register provides a mechanism by which software can direct the host controller to transmit
multiple asynchronous requests during a fairness interval. See Table 8−22 for a complete description of the register
contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Fairness control
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Fairness control
Type R R R R R R R R RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Fairness control
Offset: DCh
Type: Read-only
Default: 0000 0000h
Table 8−22. Fairness Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−8 RSVD R Reserved. Bits 31−8 return 0s when read.
7−0 pri_req RW This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY layer during a fairness interval. The default
value for this field is 00h.