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8.28 Initial Channels Available High Register
The initial channels available high register value is loaded into the corresponding bus management CSR register on
a system (hardware) or software reset. See Table 8−20 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Initial channels available high
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Initial channels available high
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Register: Initial channels available high
Offset: B4h
Type: Read/Write
Default: FFFF FFFFh
Table 8−20. Initial Channels Available High Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−0 InitChanAvailHi RW This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR
register upon a GRST, PRST, or a 1394 bus reset.
8.29 Initial Channels Available Low Register
The initial channels available low register value is loaded into the corresponding bus management CSR register on
a system (hardware) or software reset. See Table 8−21 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Initial channels available low
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Initial channels available low
Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Register: Initial channels available low
Offset: B8h
Type: Read/Write
Default: FFFF FFFFh
Table 8−21. Initial Channels Available Low Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−0 InitChanAvailLo RW This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_LO CSR
register upon a GRST, PRST, or a 1394 bus reset.