Filter
Top Products
3−12
SDA
SCL
Start
Condition
Stop
Condition
Change of
Data Allowed
Data Line Stable,
Data Valid
Figure 3−7. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low, so that it remains low during the high state of the SCL signal. Figure 3−8
illustrates the acknowledge protocol.
SCL From
Master
123 789
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3−8. Serial-Bus Protocol Acknowledge
The PCI7x21/PCI7x11 controller is a serial bus master; all other devices connected to the serial bus external to the
PCI7x21/PCI7x11 controller are slave devices. As the bus master, the PCI7x21/PCI7x11 controller drives the SCL
clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle
states.
Typically, the PCI7x21/PCI7x11 controller masters byte reads and byte writes under software control. Doubleword
reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under
software control. See Section 3.6.4, Serial-Bus EEPROM Application, for details on how the PCI7x21/PCI7x11
controller automatically loads the subsystem identification and other register defaults through a serial-bus EEPROM.
Figure 3−9 illustrates a byte write. The PCI7x21/PCI7x11 controller issues a start condition and sends the 7-bit slave
device address and the command bit zero. A 0 in the R/W
command bit indicates that the data transfer is a write. The
slave device acknowledges if it recognizes the address. If no acknowledgment is received by the PCI7x21/PCI7x11
controller, then an appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see
Section 4.50). The word address byte is then sent by the PCI7x21/PCI7x11 controller, and another slave
acknowledgment is expected. Then the PCI7x21/PCI7x11 controller delivers the data byte MSB first and expects a
final acknowledgment before issuing the stop condition.
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Slave Address Word Address
R/W
S/P = Start/Stop ConditionA = Slave Acknowledgement
b7 b6 b4b5 b3 b2 b1 b0 A P
Data Byte
Figure 3−9. Serial-Bus Protocol—Byte Write