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14−6
14.5 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS MIN MAX UNIT
t
c
Cycle time, PCLK t
cyc
30 ns
t
w(H)
Pulse duration (width), PCLK high t
high
11 ns
t
w(L)
Pulse duration (width), PCLK low t
low
11 ns
t
r
, t
f
Slew rate, PCLK ∆v/∆t 1 4 V/ns
t
w
Pulse duration (width), GRST t
rst
1 ms
t
su
Setup time, PCLK active at end of PRST t
rst-clk
100 ms
14.6 Switching Characteristics for PHY Port Interface
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Jitter, transmit Between TPA and TPB ±0.15 ns
Skew, transmit Between TPA and TPB ±0.10 ns
t
r
TP differential rise time, transmit 10% to 90%, at 1394 connector 0.5 1.2 ns
t
f
TP differential fall time, transmit 90% to 10%, at 1394 connector 0.5 1.2 ns
14.7 Operating, Timing, and Switching Characteristics of XI
PARAMETER MIN TYP MAX UNIT
V
DD
3.0 3.3 3.6 V (PLLV
CC
)
V
IH
High-level input voltage 0.63V
CC
V
V
IL
Low-level input voltage 0.33V
CC
V
Input clock frequency 24.576 MHz
Input clock frequency tolerance <100 PPM
Input slew rate 0.2 4 V/ns
Input clock duty cycle 40% 60%
14.8 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature
This data manual uses the following conventions to describe time ( t ) intervals. The format is t
A
, where subscript A
indicates the type of dynamic parameter being represented. One of the following is used: t
pd
= propagation delay time,
t
d
(t
en
, t
dis
) = delay time, t
su
= setup time, and t
h
= hold time.
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS MIN MAX UNIT
t
pd
Propagation delay time, See Note 4
PCLK-to-shared signal
valid delay time
t
val
C
L
= 50 pF,
11
ns
t
pd
Propagation delay time, See Note 4
PCLK-to-shared signal
invalid delay time
t
inv
C
L
= 50 pF,
See Note 4
2
ns
t
en
Enable time, high impedance-to-active delay time from PCLK t
on
2 ns
t
dis
Disable time, active-to-high impedance delay time from PCLK t
off
28 ns
t
su
Setup time before PCLK valid t
su
7 ns
t
h
Hold time after PCLK high t
h
0 ns
NOTE 4: PCI shared signals are AD31−AD0, C/BE3−C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.