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Epson Research and Development Page 101
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
Figure 6-41 320x240 Epson D-TFD Panel Vertical Timing
1. Ts = pixel clock period
Table 6-35: 320x240 Epson D-TFD Panel Vertical Timing
Symbol Parameter Min Typ Max Units
t1
FPFRAME pulse width 200 Ts (note 1)
t2
Horizontal total period 400 Ts
t3 Vertical display start 400 Ts
FPFRAME
Vertical Total = 250HT
FPDAT[17:0]
t1
line1
GPIO1
GPIO0
GPIO2 (FR)
(odd frame)
(even frame)
t2
line2
GPIO2 (FR)
t3
(DY)
(YSCL)
(XINH)
(R,G,B)