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Epson Research and Development Page 63
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
Note
Max frequency (f
BUSCLK
) when using crystal oscillator is 12MHz.
Table 6-14: Indirect Interface Timing (Mode 68)
Symbol Parameter Min Max Units
f
BUSCLK
Bus Clock frequency
50 MHz
T
BUSCLK
Bus Clock period
1/f
BUSCLK
ns
t1
A0 / R/W# setup to (CS# | EBU
), (CS# | EBL) falling edge
1ns
t2
A0 / R/W# hold to (CS# | EBU
), (CS# | EBL) rising edge
3ns
t3
D[15:0] setup to (CS# | EBU
) rising edge (write cycle)
1T
BUSCLK
t4
D[15:0] hold to (CS# | EBU
) rising edge (write cycle)
4ns
t5
Falling edge of (CS# | EBL
) to D[15:0] driven (read cycle)
2T
BUSCLK
t6a
Falling edge of (CS# | EBL
) to valid D[15:0] driven for MCLK = BCLK
(read cycle)
7.5 T
BUSCLK
t6b
Falling edge of (CS# | EBL
) to valid D[15:0] driven for MCLK = BCLK/2
(read cycle)
9.5 T
BUSCLK
t6c
Falling edge of (CS# | EBL
) to valid D[15:0] driven for MCLK = BCLK/3
(read cycle)
12.5 T
BUSCLK
t6d
Falling edge of (CS# | EBL
) to valid D[15:0] driven for MCLK = BCLK/4
(read cycle)
16.5 T
BUSCLK
t7
Valid D[15:0] hold to (CS# | EBL
) rising edge
0.5 T
BUSCLK
t8a
(CS# | EBU
) High pulse width (write cycle)
4T
BUSCLK
t8b
(CS# | EBL
) High pulse width for MCLK = BCLK (read cycle)
8T
BUSCLK
t8c
(CS# | EBL
) High pulse width for MCLK = BCLK/2 (read cycle)
11 T
BUSCLK
t8d
(CS# | EBL
) High pulse width for MCLK = BCLK/3 (read cycle)
15 T
BUSCLK
t8e
(CS# | EBL
) High pulse width for MCLK = BCLK/4 (read cycle)
17 T
BUSCLK
t9a
(CS# | EBL
) Low pulse width (read turnaround)
2.5 T
BUSCLK
t9b
(CS# | EBU
) Low pulse width for MCLK = BCLK (write turnaround)
2.5 T
BUSCLK
t9c
(CS# | EBU
) Low pulse width for MCLK = BCLK/2 (write turnaround)
5.5 T
BUSCLK
t9d
(CS# | EBU
) Low pulse width for MCLK = BCLK/3 (write turnaround)
7.5 T
BUSCLK
t9e
(CS# | EBU
) Low pulse width for MCLK = BCLK/4 (write turnaround)
9.5 T
BUSCLK