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Epson Research and Development Page 127
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
bits 1-0 Panel Type Select Bits[1:0]
These bits select the panel type.
bits 5-0 MOD Rate Bits [5:0]
These bits are for passive LCD panels only.
When these bits are all 0, the MOD output signal (DRDY) toggles every FPFRAME.
For a non-zero value n, the MOD output signal (DRDY) toggles every n FPLINE.
bits 6-0 Horizontal Total Bits [6:0]
These bits specify the LCD panel Horizontal Total period, in 8 pixel resolution. The Hori-
zontal Total is the sum of the Horizontal Display period and the Horizontal Non-Display
period. Since the maximum Horizontal Total is 1024 pixels, the maximum panel resolu-
tion supported is 800x600.
Horizontal Total in number of pixels = ((REG[12h] bits 6:0) + 1) × 8
Note
For TFT Type 3 panels this register must be programmed such that the following
formula is valid.
HT - HDPS - HDP < 11 PCLKs
Note
This register must be programmed such that the following formula is valid.
HDPS + HDP < HT
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 68.
Table 8-7: LCD Panel Type Selection
REG[10h] Bits[1:0] Panel Type Select
00 STN
01 TFT
10 HR-TFT
11 D-TFD
MOD Rate Register
REG[11h] Read/Write
n/a MOD Rate Bits 5-0
7 6543210
Horizontal Total Register
REG[12h] Read/Write
n/a Horizontal Total Bits 6-0
76543210