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Epson Research and Development Page 81
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
Figure 6-26 Single Color 8-Bit Panel A.C. Timing (Format 2)
1. Ts = pixel clock period
2. t1
min
= HPS + t4
min
3. t2
min
= t3
min
- (HPS + t4
min
)
4. t3
min
= HT
5. t4
min
= HPW
6. t5
min
= HPS - 1
7. t6
min
= HPS - (HDP + HDPS) + 1, if negative add t3
min
8. t14
min
= HDPS - (HPS + t4
min
), if negative add t3
min
Table 6-23: Single Color 8-Bit Panel A.C. Timing (Format 2)
Symbol Parameter Min Typ Max Units
t1 FPFRAME setup to FPLINE falling edge note 2 Ts (note 1)
t2 FPFRAME hold from FPLINE falling edge note 3 Ts
t3 FPLINE period note 4 Ts
t4 FPLINE pulse width note 5 Ts
t5 MOD transition to FPLINE rising edge note 6 Ts
t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts
t7 FPSHIFT falling edge to FPLINE falling edge t6 + t4 Ts
t8 FPLINE falling edge to FPSHIFT falling edge t14 + 2 Ts
t9 FPSHIFT period 2 Ts
t10 FPSHIFT pulse width low 1 Ts
t11 FPSHIFT pulse width high 1 Ts
t12 FPDAT[7:0] setup to FPSHIFT falling edge 1 Ts
t13 FPDAT[7:0] hold to FPSHIFT falling edge 1 Ts
t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts
t14 t10t11
t12 t13
Data Timing
FPFRAME
t1
t2
t3
t5
t4
FPLINE
DRDY (MOD)
Sync Timing
FPLINE
FPSHIFT
t8 t9
12
t7
t6
FPDAT[7:0]