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Epson Research and Development Page 27
Vancouver Design Center
Programming Notes and Examples S1D13708
Issue Date: 01/11/20 X39A-G-003-01
ADVANCE
D
IN
F
ORMATION
Subje
ct to C
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nge
6 Power Save Mode
The S1D13708 is designed for very low-power applications. During normal operation, the
internal clocks are dynamically disabled when not required. The S1D13708 design also
includes a Power Save Mode to further save power. When Power Save Mode is initiated,
LCD power sequencing is required to ensure the LCD bias power supply is disabled
properly. For further information on LCD power sequencing, see Section 6.3, “LCD Power
Sequencing” on page 29.
For Power Save Mode AC Timing, see the S1D13708 Hardware Functional Specification,
document number X39A-A-001-xx.
6.1 Overview
The S1D13708 includes a software initiated Power Save Mode. Enabling/disabling Power
Save Mode is controlled using the Power Save Mode Enable bit (REG[A0h] bit 0).
While Power Save Mode is enabled the following conditions apply.
• Registers are accessible
• Memory writes are possible
1
• Memory reads are not possible
• Look-Up Table registers are accessible.
• LCD display is inactive.
• LCD interface outputs are forced low.
Note
1
Memory writes are possible during power save mode because the S1D13708 dynami-
cally enables the memory controller for display buffer writes.