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Epson Research and Development Page 165
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
bit 4 Partial Mode Display Enable
This bit enables/disables the Partial Mode Display for the TFT Type 3 and has no effect
for all other panel interfaces.
When this bit = 1, Partial Mode Display is enabled.
When this bit = 0, Partial Mode Display is disabled.
bit 3 Partial Mode Display Type Select
This bit selects the type of partial mode display.
When this bit =0, the Stripe type of partial mode display is selected. If Stripe is enabled
only the Y Position registers are used in calculating the partial display.
When this bit = 1, type Block type of partial mode display is selected. If Block is enabled
both the X and Y Position registers are used in calculating the partial display.
bit 2 Area 2 Display Enable
This bit enables/disables the Area 2 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 2 is enabled.
When this bit = 0, Area 2 is disabled.
bit 1 Area 1 Display Enable
This bit enables/disables the Area 1 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 1 is enabled.
When this bit = 0, Area 1 is disabled.
bit 0 Area 0 Display Enable
This bit enables/disables the Area 0 for Partial Mode Display on the TFT Type 3 and has
no effect for all other panel interfaces.
When this bit = 1, Area 0 is enabled.
When this bit = 0, Area 0 is disabled.
bits 5-0 Partial Mode Display Refresh Cycle Bits [5:0]
These bits specify the refresh cycle for the Partial Mode Display. The refresh cycle can be
a value from 0 to 63. This register is used for the TFT Type 3 Interface and has no effect
for all other panel interfaces.
TFT Type 3 Partial Mode Display Area Control Register
REG[E0h] Read/Write
n/a
Partial Mode
Display
Enable
Partial Mode
Display Type
Select
Area 2
Display
Enable
Area 1
Display
Enable
Area 0
Display
Enable
7 6 543210
TFT Type 3 Partial Mode Display Refresh Cycle Register
REG[E1h] Read/Write
n/a Partial Mode Display Refresh Cycle bits 5-0
7 6543210