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Epson Research and Development Page 13
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
Figure 14-1 Memory Mapping for Ink Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 14-2 Transparent Color Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 15-1 Sample timing of “register write” with Mode 68. . . . . . . . . . . . . . . . . . . . . 190
Figure 15-2 Sample timing of “register read” with Mode 68 . . . . . . . . . . . . . . . . . . . . . 191
Figure 15-3 Sample timing of “memory write” with Mode 68, Big Endian . . . . . . . . . . . . . 192
Figure 15-4 Sample timing of “memory read” with Mode 68, Big Endian . . . . . . . . . . . . . . 194
Figure 15-5 Sample timing of “register write” for Mode 68 when Memory Access Select Enabled . 196
Figure 15-6 Sample timing of “register read” for Mode 68 when Memory Access Select Enabled . 198
Figure 15-7 Sample timing of “register write” with Mode 80. . . . . . . . . . . . . . . . . . . . . 200
Figure 15-8 Sample timing of “register read” with Mode 80 . . . . . . . . . . . . . . . . . . . . . 201
Figure 15-9 Sample timing of “memory write” with mode 80, little endian . . . . . . . . . . . . . 202
Figure 15-10Sample timing of “memory read” with mode 80, Little endian . . . . . . . . . . . . . 204
Figure 15-11Sample timing of “memory write” for Mode 80 when Memory Access Select Enabled 206
Figure 15-12Sample timing of “memory read” for Mode 80 when Memory Access Select Enabled . 208
Figure 16-1 Recommended Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 17-1 Byte-swapping for 16 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 17-2 Byte-swapping for 1/2/4/8 Bpp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 19-1 Mechanical Data PFBGA 120-pin Package . . . . . . . . . . . . . . . . . . . . . . . 215