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Epson Research and Development Page 7
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
List of Tables
Table 4-1: PFBGA 120-pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4-2: S1D13708 Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4-3: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4-4: LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 4-5: Clock Input Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4-6: Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4-7: Power And Ground Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4-8: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4-9: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 4-10: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5-1: Absolute Maximum Ratings (Preliminary - Subject to Change). . . . . . . . . . . . . . 41
Table 5-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 5-3: Electrical Characteristics for VDD = 3.3V typical. . . . . . . . . . . . . . . . . . . . . 41
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1 . . . . . . . . . . 42
Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1 . . . . . . . . . . 43
Table 6-3: Clock Input Requirements for CLKI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 6-4: Internal Clock Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 6-5: Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 6-6: Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 6-7: Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 6-8: Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 6-9: Motorola MC68K #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 6-10: Motorola MC68K #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 6-11: Motorola REDCAP2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 6-12: Motorola DragonBall Interface with DTACK Timing. . . . . . . . . . . . . . . . . . . 59
Table 6-13: Motorola DragonBall Interface without DTACK Timing . . . . . . . . . . . . . . . . . 61
Table 6-14: Indirect Interface Timing (Mode 68). . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 6-15: Indirect Interface Timing (Mode 80). . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 6-16: Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 6-17: Passive/TFT Power-Off Sequence Timing. . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 6-18: Panel Timing Parameter Definition and Register Summary . . . . . . . . . . . . . . . . 69
Table 6-19: Single Monochrome 4-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . 73
Table 6-20: Single Monochrome 8-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . 75
Table 6-21: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 79
Table 6-23: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 81
Table 6-24: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 83