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Epson Research and Development Page 11
Vancouver Design Center
13708CFG Configuration Program S1D13708
Issue Date: 01/11/16 X39A-B-001-01
Timing This field shows the actual PCLK used by the configu-
ration process.
BCLK These settings select the clock source and divisor for the
internal bus interface clock (BCLK).
Source Selects the BCLK source. Possible sources include
CLKI and XTAL. Note that XTAL can be selected only
when the indirect interface is enabled.
Divide Specifies the divide ratio for the clock source. The
divide ratio is applied to the BCLK source to derive
BCLK.
Timing This field shows the actual BCLK frequency used by
the configuration process.
MCLK These settings select the clock source and input clock
divisor for the internal memory clock (MCLK). For the
best performance, MCLK should be set as close to the
maximum (50 MHz) as possible.
Source The MCLK source is always BCLK.
Divide Specifies the divide ratio for the clock source. The
divide ratio is applied to the MCLK source to derive
MCLK.
This divide ratio should be left at 1:1 unless the
resultant MCLK is greater that 50MHz.
Timing This field shows the actual MCLK frequency used by
the configuration process.