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Epson Research and Development Page 215
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
18 Power Save Mode
A software initiated Power Save Mode is incorporated into the S1D13708 to accommodate
the need for power reduction in the hand-held devices market. This mode is enabled via the
Power Save Mode Enable bit (REG[A0h] bit 0).
Software Power Save Mode saves power by powering down the panel and stopping display
refresh accesses to the display buffer.
Note
1
When power save mode is enabled, the memory controller is powered down and the
status of the memory controller is indicated by the Memory Controller Power Save Sta-
tus bit (REG[A0h] bit 3). However, memory writes are possible during power save
mode because the S1D13708 dynamically enables the memory controller for display
buffer writes.
2
GPIO Pins are configured using the configuration pin CNF3 which is latched on the
rising edge of RESET#. For information on CNF3, see Table 4-8: “Summary of Power-
On/Reset Options,” on page 38.
3
GPIOs can be accessed and if configured as outputs can be changed.
After reset, the S1D13708 is always in Power Save Mode. Software must initialize the chip
(i.e. programs all registers) and then clear the Power Save Mode Enable bit.
Table 18-1: Power Save Mode Function Summary
Software
Power Save
Normal
IO Access Possible? Yes Yes
Memory Writes Possible? Yes
1
Yes
Memory Reads Possible? No
1
Yes
Look-Up Table Registers Access Possible? Yes Yes
Display Active? No Yes
LCD Interface Outputs Forced Low Active
PWMCLK Stopped Active
GPIO Pins configured for HR-TFT/D-TFD/TFT Type 2/3
2
Forced Low Active
GPIO Pins configured as GPIOs Access Possible? Yes
3
Yes