Filter
Top Products
Page 28 Epson Research and Development
Vancouver Design Center
S1D13708 Programming Notes and Examples
X39A-G-003-01 Issue Date: 01/11/20
ADVANCE
D
IN
F
ORMATION
Subje
ct to C
ha
nge
6.2 Registers
6.2.1 Power Save Mode Enable
The Power Save Mode Enable bit initiates Power Save Mode when set to 1. Setting the bit
to 0 disables Power Save Mode and returns the S1D13708 to normal mode. At reset this bit
is set to 1.
Note
Enabling/disabling Power Save Mode requires proper LCD Power Sequencing. See Sec-
tion 6.3, “LCD Power Sequencing” on page 29.
6.2.2 Memory Controller Power Save Status
The Memory Controller Power Save Status bit is a read-only status bit which indicates the
power save state of the S1D13708 SRAM interface. When this bit returns a 1, the SRAM
interface is powered down and the memory clock source may be disabled. When this bit
returns a 0, the SRAM interface is active. This bit returns a 0 after a chip reset.
Note
Memory writes are possible during power save mode because the S1D13708 dynamical-
ly enables the memory controller for display buffer writes.
Power Save Configuration Register
REG[A0h] Read/Write
Vertical Non-
Display
Period Status
(RO)
n/a
Memory
Controller
Power Save
Status (RO)
n/a
Power Save
Mode Enable
7 6 5 432 10
Power Save Configuration Register
REG[A0h] Read/Write
Vertical Non-
Display
Period Status
(RO)
n/a
Memory
Controller
Power Save
Status (RO)
n/a
Power Save
Mode Enable
7 6 5 432 10