Filter
Top Products
Epson Research and Development Page 87
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. Ts = pixel clock period
2. t6min = HDPS - HPS if negative add HT
3. t8min = HPS - (HDP + HDPS) if negative add HT
Table 6-25: TFT A.C. Timing
Symbol Parameter Min Typ Max Units
t1
FPFRAME cycle time VT Lines
t2
FPFRAME pulse width low VPW Lines
t3
FPFRAME falling edge to FPLINE falling edge phase difference HPS Ts (note 1)
t4
FPLINE cycle time HT Ts
t5
FPLINE pulse width low HPW Ts
t6
FPLINE Falling edge to DRDY active note 2 250 Ts
t7
DRDY pulse width HDP Ts
t8 DRDY falling edge to FPLINE falling edge note 3 Ts
t9 FPSHIFT period 1 Ts
t10 FPSHIFT pulse width high 0.5 Ts
t11 FPSHIFT pulse width low 0.5 Ts
t12 FPLINE setup to FPSHIFT falling edge 0.5 Ts
t13 DRDY to FPSHIFT falling edge setup time 0.5 Ts
t14 DRDY hold from FPSHIFT falling edge 0.5 Ts
t15 Data setup to FPSHIFT falling edge 0.5 Ts
t16 Data hold from FPSHIFT falling edge 0.5 Ts