Filter
Top Products
Page 210 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
arrangement for word accesses only.
The S1D13708 indirect interface implements an auto increment function to allow
burst memory accesses. For byte accesses, the Memory Address Pointer registers
(REG[C0h], REG[C1h], REG[C2h]) are automatically incremented “+1”. For word
accesses, the Memory Address Pointer registers are automatically incremented “+2”.
Note
If the Memory Access Select bit is enabled (REG[C6h] bit 0 = 1), all memory accesses
are word accesses (RDU# is ignored). Therefore, the memory address set in REG[C0h]
through REG[C2h] must be an even address.
15.3 Limitations
Each Indirect cycle requires a certain number of BCLK cycles to setup/complete (refer to
Indirect Interface Timing (Mode 68) on page 62 and Indirect Interface Timing (Mode 80)
on page 64). The BCLK source can be derived from either XTAL or CLKI. When XTAL
is used, and has a different frequency than the CPU, the CPU must take the speed difference
into account and change the cycle time accordingly.
Example: If the CPU clock is running at 20MHz and the S1D13708 is running with a
10MHz crystal, referring to Table 6-14, item t6a requires 7.5 BUSCLKs. Since the CPU
will be running 2 times faster than BUSCLK, t6a will require to be doubled to15
BUSCLKs.