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Epson Research and Development Page 107
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
Figure 6-45 TFT Type 3 Vertical Timing
FPFRAME
GPIO0
GPIO1
D[17:0]
Line2Line1
t1
t2
t3
t4
t6
Last
GPIO5
GPIO2
t3
t7
FPLINE
t5
(Odd Frame)
(Even Frame)
(Odd Frame)
(Even Frame)
t5
(STV)
(CPV)
(LP)
(OE)
(XOEV)
(POL)
GPIO2
(POL)
GPIO2
(VCOM)
GPIO2
(VCOM)