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Epson Research and Development Page 111
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
1. Ts = pixel clock period
2. t1typ = (REG[19h] bits 1-0, REG[18h] bits 7-0) +1
3. t2typ = (REG[24h] bits 2-0) + 1
4. t3typ = (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
5. t4typ = ((REG[12h] bits 6-0) + 1) x 8
6. t5typ = (REG[12h] bits 6-0) + 1
7. t6typ = HDPS- (HPS + 1) x 8
8. t8typ = ((REG[14h] bits 6-0) + 1) x 8
9. t9typ = HPS - HDPS - HDP
Table 6-40: TFT Type 4 A.C. Timing
Symbol Parameter Min Typ Max Units
t1
FPFRAME cycle time VT note 2 Lines
t2
FPFRAME pulse width low VPW note 3 Lines
t3
FPFRAME falling edge to FPLINE falling edge phase difference HPS note 4 Ts (note 1)
t4
FPLINE cycle time HT note 5 Ts
t5
FPLINE pulse width low HPW note 6 Ts
t6
FPLINE Falling edge to DRDY active note 7 250 Ts
t7 DRDY active to data setup 8 Ts
t8
DRDY pulse width HDP note 8 Ts
t9 DRDY falling edge to FPLINE falling edge note 9 Ts
t10 FPSHIFT period 1 Ts
t11 FPSHIFT pulse width high 0.5 Ts
t12 FPSHIFT pulse width low 0.5 Ts
t13 FPLINE setup to FPSHIFT falling edge 0.5 Ts
t14 DRDY to FPSHIFT falling edge setup time 0.5 Ts
t15 DRDY hold from FPSHIFT falling edge 0.5 Ts
t16 Data setup to FPSHIFT falling edge 0.5 Ts
t17 Data hold from FPSHIFT falling edge 0.5 Ts