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Epson Research and Development Page 203
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
The following shows an example of a “memory write” with Mode 80, little endian.
Figure 15-9 Sample timing of “memory write” with mode 80, little endian
1. write register number of Memory Access Pointer 0 (REG[C0h]) (command write).
2. write memory address 0 to the high byte and memory address 1 to the low byte
(MA[15:0]) (data write).
3. write register number of Memory Access Pointer 2 (REG[C2h]) (command write).
4. write memory address 2 (MA16) to the low byte (data write).
5. write register number of Memory Access Start register (REG[C4h]) (command write).
Note
No “data write” is required after a command write to the Memory Access Start register
(REG[C4h]). This step configures the S1D13708 for burst memory access beginning
with the next data write.
A0
CS#
WRU#
WRL#
RDU#
RDL#
D[7:0]
D[15:8]
REG[C0h]
Data Write
word access
Command
Data Write
byte access
even number
memory data
Data Write
Data Write
Data Write Data Write Data Write
word access
byte access
byte access
memory data
memory data memory data
Address +1
word access
byte access
memory data
even address
even address
odd address
even address
even address
Write
Command
Write
Command
Write
REG[C4h]
REG[C2h]
even number
(byte)
Address +1
(byte)
Address +2
(word)
Address +2
(word)
1 2 3 4 5 6 6 6 6 6
STEP