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Page 16 Epson Research and Development
Vancouver Design Center
S1D13708 13708CFG Configuration Program
X39A-B-001-01 Issue Date: 01/11/16
displayed image by fine tuning the horizontal and
vertical display totals.
The display total equals the display period plus the non-
display period. Refer to S1D13708 Hardware
Functional Specification, document number X39A-A-
001-xx, for a complete description of the Display Total
settings.
Display Start It is recommended that the automatically generated
Display Start values be used. However, manual
adjustment may be used to improve the quality of the
displayed image by fine tuning the horizontal and
vertical display start positions.
Refer to S1D13708 Hardware Functional Specifi-
cation, document number X39A-A-001-xx, for a
complete description of the Display Start settings.
Frame Rate The Frame Rate (in Hz) is calculated and displayed
based on the current settings as selected on the various
tabs. If the resulting Frame Rate is not acceptable,
adjust the settings to change the frame rate.
Panel dimensions are fixed therefore frame rate can
only be adjusted by changing either PCLK or display
total values.
Pixel Clock Select the desired Pixel Clock (in MHz) from the drop-
down list. The range of frequencies displayed is
dependent on the PCLK source and divide settings as
selected on the Clocks tab.
HRTC/FPLINE (pixels) These settings allow fine tuning of the TFT line pulse
parameters. Refer to S1D13708 Hardware Functional
Specification, document number X39A-A-001-xx for a
complete description of the FPLINE pulse settings.
Start pos Specifies the delay (in pixels) from the start of the
horizontal non-display period to the leading edge of the
FPLINE pulse.
Pulse Width Specifies the width (in pixels) of the horizontal sync
signal (FPLINE).